1. Field
Exemplary embodiments of the present invention relate to an equalizer circuit and a receiver circuit including the same.
2. Description of the Related Art
In electrical systems, a signal is transmitted within an integrated circuit (IC) chip or between two or more IC chips. When a signal is transmitted between two or more IC chips, the signal may be transmitted through a transmission line, a cable, or other means on a printed circuit board (PCB). Furthermore, even when a signal is transmitted within an IC chip, the signal may be transmitted through a line within the chip. When a signal is transmitted from a transmitting terminal to a receiving terminal, a signal loss occurs. Therefore, in many cases, a circuit to compensate for the signal loss may be provided at the receiving terminal.
An equalizer or a continuous time linear equalizer (CTLE) circuit compensates for the signal loss during high speed signal transmission. FIG. 1 is a diagram illustrating frequency responses of a channel 101, an equalizer 102, and a signal 103 recovered by the equalizer. In FIG. 1, the frequency response 101 of the channel represents a signal loss in the channel (signal transmission line). As the frequency of a transmitted signal increases, the signal loss gradually increases. The frequency response 102 of the equalizer represents a frequency response characteristic of the equalizer. The equalizer is designed to have a high gain as the frequency of a signal increases. The frequency response 103 represents a frequency response characteristic of the signal recovered by the equalizer. While the signal loss on the channel increases v with the increase in frequency of the signal, the gain of the equalizer increases with the increase in frequency of the signal. Thus, the signal recovered by the equalizer has a constant response characteristic in a wide frequency band.
FIG. 2 is a configuration diagram of a conventional equalizer 200.
Referring to FIG. 2, the equalizer 200 includes resistors 201 to 207 and capacitors 208 and 209. The equalizer 200 equalizes input signals IN and INB of a first terminal IN and a second terminal INB. A differential amplifier 210 differentially amplifies the equalized signals IN_E and INB_B and senses the levels of the input signals IN and INB.
The frequency response characteristic of the equalizer 200 is controlled by resistance values Rvar of variable resistors 204 and 205. By adjusting the resistance values Rvar of the variable resistors 204 and 205, the frequency response characteristic of the equalizer 200 is optimized as the frequency response 102 of the equalizer indicated in FIG. 1, which compensates for the signal loss 101 in the channel as indicated in FIG. 1. Adjustment of the resistance values of the variable resistors 204 and 205 changes not only the frequency response characteristic of the equalizer 200 but also the voltage levels of the equalized signals IN_E and INB_E. FIG. 3 illustrates low voltage value of the signals IN_E and INB_E according to the resistance values Rvar of the variable resistors 204 and 205. The low voltage value indicates voltage value of the equalized signals IN_E and INB_E when the signals IN_E and INB_E are of a low level. Referring to FIG. 3, it can be seen that, as the resistance values Rvar of the variable resistors 204 and 205 increase, the voltage level of the equalized signals IN_E and INB_E decreases.
The change of voltage levels of the equalized signals IN_E and INB_E has no influence on a fully-differential system in which the voltage level of the equalized input signal bar INB_E is changed together with the variation in voltage level of the equalized input signal IN_E.
However, the variation in voltage level of the equalized input signal IN_E may raise a concern in a pseudo-differential system transmitting the input signal IN in a single-ended manner and using a reference voltage VREF to determine the logic value of the input signal IN. That is because the variation of the level of the equalized input signal IN_E without change of the level of the reference voltage VREF may raise a concern in determining the logic level of the input signal IN. Equalizing the reference voltage VREF is not a solution to such a concern. A large amount of current inevitably passes through the equalizer 200 because of termination resistors 201, 204, and 205, which makes the reference voltage VREF difficult to be equalized by the equalizer 200, because the reference voltage VREF supplied from the pseudo-differential system is driven through a very weak current, which corresponds to a several tenths of the driving current of the input signals IN and INB.
In short, it is not appropriate to use the equalizer 200 in the pseudo-differential system because variation of the voltage level of the equalized input signal IN_E is inevitable in adjusting of the equalizer 200 while it is not appropriate to equalize the reference voltage VREF by the equalizer 200.